An Intelligent Instrumentation SoC with Adaptive-TSN Architecture: Architecture and Hardware Figures

Abstract

Elham Khalesi

This paper presents the architectural and board-level hardware documentation of an intelligent instrumentation System-on-Chip (SoC) that couples an in-line fixed-point polynomial calibration accelerator with a fully hardwired IEEE 802.1Qbv Time-Sensitive Networking (TSN) engine 1. A custom RV32IMAC RISC-V core supervises an AXI4-Lite fabric connecting a 6-stage Horner calibration pipeline (Q8.24 arithmetic, 60 ns fixed latency) and an 8-queue Gate Control List (GCL) scheduler implementing the Time-Aware Shaper defined in IEEE Std 802.1Qbv-2015 1. Post-layout validation achieved an effective resolution of 16.91 bits, an 84.1× reduction in residual thermal drift, a mean end-to- end TSN latency of 14.39 μs with zero deadline violations, and an 87.35% reduction in per-sample energy (41.75 μJ), as documented in the project’s validated simulation deliverables 2. This paper integrates the complete visual asset set — the top-level SoC block diagram, the subsystem data path microarchitecture, the board-level hardware schematic, a conceptual device render, and the comprehensive simulation report — directly into the paper body as Figures. 1–5 2.

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