Design, Physical Analysis, and Area Scaling Assessment of a 2 nm Single-Fin FinFET with Monolithic Self-Aligned Nanowire Interconnects

Abstract

Elham Khalesi

This paper presents the design, physical analysis, and area-scaling assessment of a 2 nm single-fin FinFET in which the source/drain regions are extended into monolithic, epitaxially continuous silicon nanowires that double as local interconnects. The nanowire extensions are patterned in the same lithographic and etch step as the fin itself, producing a fully self-aligned, via-less middle-of-line (MOL) integration scheme on an UTB-SOI/SIMOX substrate. Analytical layout comparison against a conventional 2 nm FinFET cell with V0/VD contacts shows a 25–30% reduction in standard-cell area (28% for the reference inverter cell) and a 35–40% reduction in MOL volume, together with an estimated 30% reduction in gate–source/drain overlap capacitance and roughly 34% lower RC gate delay. The tri-gate device concept on which this architecture builds was established in early SOI-based patents on tri-gate devices and fabrication methods (US6858478B2). The results indicate that replacing vertical metal contacts with self-aligned monolithic nanowire extensions is a credible path to cell-area scaling beyond the limits imposed by conventional contact/via modules.

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